Content addressable memories (CAM) are used to compare input words to all words stored in the memory. If the input word matches one or more words stored in the memory, the CAM will output the address of one of the matched words. In some CAM applications, it is important to know if a “match” result is a single-hit or multiple-hit. For this, a multiple match detect circuit must be used with such CAMs.
Prior multiple match detect circuits included dynamic analog comparator circuits that measured a signal value that was based on the number of hits. The worst-case condition of such circuits was to distinguish between one and two hits, since the difference between those two cases was the smallest.
As semiconductor technology advances toward smaller transistors, process variations of manufacturing semiconductor chips affects transistor performance in relatively greater proportion. In 0.13μ and newer integrated circuit technologies, the effects of process variation is relatively large compared to older, larger technologies. Therefore, it is more difficult to distinguish between one and two hits with an analog comparator with newer, smaller technologies. One problem of analog comparator circuits is that they do not consistently operate across all PVT corners (i.e. different combinations of process, voltage and temperatures). For example, inconsistency is known to exist in chips constructed using 0.18μ technology. The ability to form reliable analog comparators in 0.13μ and newer technology is even more problematic due to the sensitivity of the chip to process variations.
FIG. 1 illustrates a prior multiple match detect circuit for a CAM containing N words and constructed in 0.18μ or larger technology. Individual hitlines HL0-HL[N-1] carry the compare results of individual words in the CAM to the input word; the hitline carrying a signal representing that the corresponding word in the CAM matches the input word. Hitlines HL0-HL[N-1] are connected to two dedicated bitlines, X1N and X1 through respective pull-down transistors 10 and respective pull-up transistors 12. When a hit signal appears on any of the hitlines HL0-HL[N-1], the respective pull-down and pull-up transistors will be turned on. Thus if one hit occurs, one pull-down and one pull-up transistors are turned on; if there are two hits, two pull-down and two pull-up transistors will be turned on, and so on. Bitlines X1N and X1 are connected to analog comparator 14, which distinguishes between one and two hits according to different pull-up and pull-down strengths.
One problem with prior analog multiple match detect circuits is that as the technology moves to smaller transistors, such as 0.18μ and smaller, it becomes difficult to find a working point for the comparator to distinguish one and two hits across all PVT corners. The circuit would be too sensitive to process variations that the confidence is not great that multiple hits in a CAM would be detected using 0.13μ technology.
Another disadvantage with some multiple hit detection circuits is that they are not designed to identify multiple hits simultaneously with the identification of general hits, an identification of a general hit being that there is at least one hit in alliwords of the memory. More particularly, all CAMs are designed to identify general hits, but separate circuitry is required to identify multiple hits.
Yet another disadvantage with analog comparator circuits used for multiple match detection is that the comparator circuit must operate on a clock signal, which causes timing or race condition issues that must be addressed with timing margins. The addition of timing margins usually slows circuit performance, thereby contributing to delay.